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32 Mbit (x16) Multi-Purpose Flash
SST39VF320
SST39VF3202.7V 32Mb (x16) MPF memory
Preliminary Specifications
FEATURES:
* Organized as 2M x16 * Single 2.7-3.6V Read and Write Operations * Superior Reliability - Endurance: 100,000 Cycles (typical) - Greater than 100 years Data Retention * Low Power Consumption (typical values at 5 MHz) - Active Current: 9 mA (typical) - Standby Current: 3 A (typical) - Auto Low Power Mode: 3 A (typical) * Sector-Erase Capability - Uniform 2 KWord sectors * Block-Erase Capability - Uniform 32 KWord blocks * Fast Read Access Time - 70 ns - 90 ns * Latched Address and Data * Fast Erase and Word-Program - Sector-Erase Time: 18 ms (typical) - Block-Erase Time: 18 ms (typical) - Chip-Erase Time: 40 ms (typical) - Word-Program Time: 7 s (typical) - Chip Rewrite Time: 15 seconds (typical) * Automatic Write Timing - Internal VPP Generation * End-of-Write Detection - Toggle Bit - Data# Polling * CMOS I/O Compatibility * JEDEC Standard - Flash EEPROM Pinouts and command sets * Packages Available - 48-lead TSOP (12mm x 20mm) - 48-ball TFBGA (6mm x 8mm)
PRODUCT DESCRIPTION
The SST39VF320 devices are 2M x16 CMOS Multi-Purpose Flash (MPF) manufactured with SST's proprietary, high performance CMOS SuperFlash technology. The split-gate cell design and thick-oxide tunneling injector attain better reliability and manufacturability compared with alternate approaches. The SST39VF320 write (Program or Erase) with a 2.7-3.6V power supply. Featuring high performance Word-Program, the SST39VF320 devices provide a typical Word-Program time of 7 sec. The devices use Toggle Bit or Data# Polling to indicate the completion of Program operation. To protect against inadvertent write, these devices have on-chip hardware and software data protection schemes. Designed, manufactured, and tested for a wide spectrum of applications, the SST39VF320 are offered with a guaranteed typical endurance of 100,000 cycles. Data retention is rated at greater than 100 years. The SST39VF320 devices are suited for applications that require convenient and economical updating of program, configuration, or data memory. For all system applications, the SST39VF320 significantly improve performance and reliability, while lowering power consumption. The SST39VF320 inherently use less energy during Erase and Program than alternative flash technologies. The total energy consumed is a function of the applied voltage, current, and time of application. Since for any given voltage range, the SuperFlash technology uses less current to pro(c)2003 Silicon Storage Technology, Inc. S71143-02-000 11/03 1
gram and has a shorter erase time, the total energy consumed during any Erase or Program operation is less than alternative flash technologies. The devices also improve flexibility while lowering the cost for program, data, and configuration storage applications. The SuperFlash technology provides fixed Erase and Program times, independent of the number of Erase/Program cycles that have occurred. Therefore the system software or hardware does not have to be modified or de-rated as is necessary with alternative flash technologies, whose Erase and Program times increase with accumulated Erase/Program cycles. To meet high density, surface mount requirements, the SST39VF320 is offered in 48-lead TSOP and 48-ball TFBGA packages. See Figures 1 and 2 for pinouts.
Device Operation
Commands are used to initiate the memory operation functions of the device. Commands are written to the device using standard microprocessor write sequences. A command is written by asserting WE# low while keeping CE# low. The address bus is latched on the falling edge of WE# or CE#, whichever occurs last. The data bus is latched on the rising edge of WE# or CE#, whichever occurs first.
The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. MPF is a trademark of Silicon Storage Technology, Inc. These specifications are subject to change without notice.
32 Mbit Multi-Purpose Flash SST39VF320
Preliminary Specifications The SST39VF320 also have the Auto Low Power mode which puts the device in a near standby mode after data has been accessed with a valid Read operation. This reduces the IDD active read current from typically 9 mA to typically 3 A. The Auto Low Power mode reduces the typical IDD active read current to the range of 2 mA/MHz of read cycle time. The device exits the Auto Low Power mode with any address transition or control signal transition used to initiate another Read cycle, with no access time penalty. Note that the device does not enter Auto Low Power mode after power-up with CE# held steadily low until the first address transition or CE# is driven high. is based on uniform block size of 32 KWord. The SectorErase operation is initiated by executing a six-byte command sequence with Sector-Erase command (30H) and sector address (SA) in the last bus cycle. The Block-Erase operation is initiated by executing a six-byte command sequence with Block-Erase command (50H) and block address (BA) in the last bus cycle. The sector or block address is latched on the falling edge of the sixth WE# pulse, while the command (30H or 50H) is latched on the rising edge of the sixth WE# pulse. The internal Erase operation begins after the sixth WE# pulse. The End-ofErase operation can be determined using either Data# Polling or Toggle Bit methods. See Figures 9 and 10 for timing waveforms. Any commands issued during the Sectoror Block-Erase operation are ignored.
Read
The Read operation of the SST39VF320 is controlled by CE# and OE#, both have to be low for the system to obtain data from the outputs. CE# is used for device selection. When CE# is high, the chip is deselected and only standby power is consumed. OE# is the output control and is used to gate data from the output pins. The data bus is in high impedance state when either CE# or OE# is high. Refer to the Read cycle timing diagram for further details (Figure 3).
Chip-Erase Operation
The SST39VF320 provide a Chip-Erase operation, which allows the user to erase the entire memory array to the "1" state. This is useful when the entire device must be quickly erased. The Chip-Erase operation is initiated by executing a sixbyte command sequence with Chip-Erase command (10H) at address 5555H in the last byte sequence. The Erase operation begins with the rising edge of the sixth WE# or CE#, whichever occurs first. During the Erase operation, the only valid read is Toggle Bit or Data# Polling. See Table 4 for the command sequence, Figure 8 for timing diagram, and Figure 19 for the flowchart. Any commands issued during the Chip-Erase operation are ignored.
Word-Program Operation
The SST39VF320 are programmed on a word-by-word basis. Before programming, the sector where the word exists must be fully erased. The Program operation is accomplished in three steps. The first step is the three-byte load sequence for Software Data Protection. The second step is to load word address and word data. During the Word-Program operation, the addresses are latched on the falling edge of either CE# or WE#, whichever occurs last. The data is latched on the rising edge of either CE# or WE#, whichever occurs first. The third step is the internal Program operation which is initiated after the rising edge of the fourth WE# or CE#, whichever occurs first. The Program operation, once initiated, will be completed within 10 s. See Figures 4 and 5 for WE# and CE# controlled Program operation timing diagrams and Figure 16 for flowcharts. During the Program operation, the only valid reads are Data# Polling and Toggle Bit. During the internal Program operation, the host is free to perform additional tasks. Any commands issued during the internal Program operation are ignored.
Write Operation Status Detection
The SST39VF320 provide two software means to detect the completion of a Write (Program or Erase) cycle, in order to optimize the system Write cycle time. The software detection includes two status bits: Data# Polling (DQ7) and Toggle Bit (DQ6). The End-of-Write detection mode is enabled after the rising edge of WE#, which initiates the internal Program or Erase operation. The actual completion of the nonvolatile write is asynchronous with the system; therefore, either a Data# Polling or Toggle Bit read may be simultaneous with the completion of the write cycle. If this occurs, the system may possibly get an erroneous result, i.e., valid data may appear to conflict with either DQ7 or DQ6. In order to prevent spurious rejection, if an erroneous result occurs, the software routine should include a loop to read the accessed location an additional two (2) times. If both reads are valid, then the device has completed the Write cycle, otherwise the rejection is valid.
Sector/Block-Erase Operation
The Sector- (or Block-) Erase operation allows the system to erase the device on a sector-by-sector (or block-byblock) basis. The SST39VF320 offer both Sector-Erase and Block-Erase modes. The sector architecture is based on uniform sector size of 2 KWord. The Block-Erase mode
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32 Mbit Multi-Purpose Flash SST39VF320
Preliminary Specifications
Data# Polling (DQ7)
When the SST39VF320 are in the internal Program operation, any attempt to read DQ7 will produce the complement of the true data. Once the Program operation is completed, DQ7 will produce true data. Note that even though DQ7 may have valid data immediately following the completion of an internal Write operation, the remaining data outputs may still be invalid: valid data on the entire data bus will appear in subsequent successive Read cycles after an interval of 1 s. During internal Erase operation, any attempt to read DQ7 will produce a `0'. Once the internal Erase operation is completed, DQ7 will produce a `1'. The Data# Polling is valid after the rising edge of fourth WE# (or CE#) pulse for Program operation. For Sector-, Block- or Chip-Erase, the Data# Polling is valid after the rising edge of sixth WE# (or CE#) pulse. See Figure 6 for Data# Polling timing diagram and Figure 17 for a flowchart.
Write operations, e.g., during the system power-up or power-down. Any Erase operation requires the inclusion of six-byte sequence. This group of devices are shipped with the Software Data Protection permanently enabled. See Table 4 for the specific software command codes. During SDP command sequence, invalid commands will abort the device to Read mode within TRC. The contents of DQ15-DQ8 can be VIL or VIH, but no other value, during any SDP command sequence.
Common Flash Memory Interface (CFI)
The SST39VF320 also contain the CFI information to describe the characteristics of the device. In order to enter the CFI Query mode, the system must load the three-byte sequence, similar to the Software ID Entry command. The last byte cycle of this command loads 98H (CFI Query command) to address 5555H. Once the device enters the CFI Query mode, the system can read CFI data at the addresses given in Tables 5 through 7. The system must write the CFI Exit command to return to Read mode from the CFI Query mode.
Toggle Bit (DQ6)
During the internal Program or Erase operation, any consecutive attempts to read DQ6 will produce alternating 1s and 0s, i.e., toggling between 1 and 0. When the internal Program or Erase operation is completed, the DQ6 bit will stop toggling. The Toggle Bit is valid after the rising edge of fourth WE# (or CE#) pulse for Program operation. For Sector-, Block- or Chip-Erase, the Toggle Bit is valid after the rising edge of sixth WE# (or CE#) pulse. See Figure 7 for Toggle Bit timing diagram and Figure 17 for a flowchart.
Product Identification
The Product Identification mode identifies the devices as the SST39VF320 and manufacturer as SST. This mode may be accessed by software operations. Users may use the Software Product Identification operation to identify the part (i.e., using the device ID) when using multiple manufacturers in the same socket. For details, see Table 4 for software operation, Figure 11 for the Software ID Entry and Read timing diagram, and Figure 18 for the Software ID Entry command sequence flowchart. TABLE 1: PRODUCT IDENTIFICATION
Address Manufacturer's ID Device ID SST39VF320 0001H 2783H
T1.1 1143
Data Protection
The SST39VF320 provide both hardware and software features to protect nonvolatile data from inadvertent writes.
Hardware Data Protection
Noise/Glitch Protection: A WE# or CE# pulse of less than 5 ns will not initiate a write cycle. VDD Power Up/Down Detection: The Write operation is inhibited when VDD is less than 1.5V. Write Inhibit Mode: Forcing OE# low, CE# high, or WE# high will inhibit the Write operation. This prevents inadvertent writes during power-up or power-down.
Data 00BFH
0000H
Product Identification Mode Exit/ CFI Mode Exit
In order to return to the standard Read mode, the Software Product Identification mode must be exited. Exit is accomplished by issuing the Software ID Exit command sequence, which returns the device to the Read mode. This command may also be used to reset the device to the Read mode after any inadvertent transient condition that apparently causes the device to behave abnormally, e.g., not read correctly. Please note that the Software ID Exit/
S71143-02-000 11/03
Software Data Protection (SDP)
The SST39VF320 provide the JEDEC approved Software Data Protection scheme for all data alteration operations, i.e., Program and Erase. Any Program operation requires the inclusion of the three-byte sequence. The three-byte load sequence is used to initiate the Program operation, providing optimal protection from inadvertent
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32 Mbit Multi-Purpose Flash SST39VF320
Preliminary Specifications CFI Exit command is ignored during an internal Program or Erase operation. See Table 4 for software command codes, Figure 13 for timing waveform, and Figure 18 for a flowchart.
FUNCTIONAL BLOCK DIAGRAM
X-Decoder
SuperFlash Memory
Memory Address
Address Buffer & Latches Y-Decoder
CE# OE# WE# DQ15 - DQ0
1143 B1.1
Control Logic
I/O Buffers and Data Latches
SST39VF320 A15 A14 A13 A12 A11 A10 A9 A8 A19 A20 WE# NC NC NC NC A18 A17 A7 A6 A5 A4 A3 A2 A1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
SST39VF320 A16 NC VSS DQ15 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VDD DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 OE# VSS CE# A0
Standard Pinout Top View Die Up
SST39VF320
1143 48-tsop EK P01.10
FIGURE 1: PIN ASSIGNMENTS FOR 48-LEAD TSOP
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32 Mbit Multi-Purpose Flash SST39VF320
Preliminary Specifications
TOP VIEW (balls facing down)
SST39VF320
6 5 4 3 2 1
A13 A9 WE# NC A7 A3
A12 A8 NC NC A17 A4
A14 A10 NC A18 A6 A2
A15 A11 A19 A20 A5 A1
A16
NC DQ15 VSS
DQ7 DQ14 DQ13 DQ6 DQ5 DQ12 VDD DQ4 DQ2 DQ10 DQ11 DQ3 DQ0 DQ8 DQ9 DQ1 A0 CE# OE# VSS 1143 48-tfbga B3K P02a.3
A
B
C
D
E
F
G
H
FIGURE 2: PIN ASSIGNMENTS FOR 48-BALL TFBGA TABLE 2: PIN DESCRIPTION
Symbol A20-A0 DQ15-DQ0 Pin Name Address Inputs Data Input/output Functions To provide memory addresses. During Sector-Erase A20-A11 address lines will select the sector. During Block-Erase A20-A15 address lines will select the block. To output data during Read cycles and receive input data during Write cycles. Data is internally latched during a Write cycle. The outputs are in tri-state when OE# or CE# is high. To activate the device when CE# is low. To gate the data output buffers. To control the Write operations. To provide power supply voltage: Unconnected pins.
T2.2 1143
CE# OE# WE# VDD VSS NC
Chip Enable Output Enable Write Enable Power Supply Ground No Connection
2.7-3.6V for SST39VF320
TABLE 3: OPERATION MODES SELECTION
Mode Read Program Erase Standby Write Inhibit Product Identification Software Mode VIL VIL VIH See Table 4
T3.1 1143
CE# VIL VIL VIL VIH X X
OE# VIL VIH VIH X VIL X
WE# VIH VIL VIL X X VIH
DQ DOUT DIN X1 High Z High Z/ DOUT High Z/ DOUT
Address AIN AIN Sector or Block address, XXH for Chip-Erase X X X
1. X can be VIL or VIH, but no other value
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32 Mbit Multi-Purpose Flash SST39VF320
Preliminary Specifications TABLE 4: SOFTWARE COMMAND SEQUENCE
Command Sequence Word-Program Sector-Erase Block-Erase Chip-Erase Software ID Software ID /CFI Exit Entry5,6 Exit7 CFI Query Entry5 1st Bus Write Cycle Addr1 5555H 5555H 5555H 5555H 5555H 5555H XXH 5555H Data2 AAH AAH AAH AAH AAH AAH F0H AAH 2AAAH 55H 5555H F0H
T4.4 1143
2nd Bus Write Cycle Addr1 2AAAH 2AAAH 2AAAH 2AAAH 2AAAH 2AAAH Data2 55H 55H 55H 55H 55H 55H
3rd Bus Write Cycle Addr1 5555H 5555H 5555H 5555H 5555H 5555H Data2 A0H 80H 80H 80H 90H 98H
4th Bus Write Cycle Addr1 WA3 5555H 5555H 5555H Data2 Data AAH AAH AAH
5th Bus Write Cycle Addr1 2AAAH 2AAAH 2AAAH Data2 55H 55H 55H
6th Bus Write Cycle Addr1 SAX4 BAX4 5555H Data2 30H 50H 10H
Software ID Exit7 /CFI Exit
1. Address format A14-A0 (Hex), Addresses AMS-A15 can be VIL or VIH, but no other value, for the Command sequence AMS = Most significant address AMS = A20 for SST39VF320 2. DQ15 - DQ8 can be VIL or VIH, but no other value, for the Command sequence 3. WA = Program word address 4. SAX for Sector-Erase; uses AMS-A11 address lines BAX, for Block-Erase; uses AMS-A15 address lines 5. The device does not remain in Software Product ID Mode if powered down. 6. With AMS-A1 =0; SST Manufacturer's ID= 00BFH, is read with A0 = 0, SST39VF320 Device ID = 2783H, is read with A0 = 1. 7. Both Software ID Exit operations are equivalent
TABLE 5: CFI QUERY IDENTIFICATION STRING1 FOR SST39VF320
Address 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH Data 0051H 0052H 0059H 0001H 0007H 0000H 0000H 0000H 0000H 0000H 0000H Data Query Unique ASCII string "QRY"
Primary OEM command set Address for Primary Extended Table Alternate OEM command set (00H = none exists) Address for Alternate OEM extended Table (00H = none exits)
T5.1 1143
1. Refer to CFI publication 100 for more details.
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32 Mbit Multi-Purpose Flash SST39VF320
Preliminary Specifications TABLE 6: SYSTEM INTERFACE INFORMATION
Address 1BH 1CH 1DH 1EH 1FH 20H 21H 22H 23H 24H 25H 26H Data 0027H 0036H 0000H 0000H 0003H 0000H 0004H 0005H 0001H 0000H 0001H 0001H Data VDD Min (Program/Erase) DQ7-DQ4: Volts, DQ3-DQ0: 100 millivolts VDD Max (Program/Erase) DQ7-DQ4: Volts, DQ3-DQ0: 100 millivolts VPP Min (00H = no VPP pin) VPP max (00H = no VPP pin) Typical time out for Word-Program 2N s (23 = 8 s) Typical time out for min size buffer program 2N s (00H = not supported) Typical time out for individual Sector/Block-Erase 2N ms (24 = 16 ms) Typical time out for Chip-Erase 2N ms (25 = 32 ms) Maximum time out for Word-Program 2N times typical (21 x 23 = 16 s) Maximum time out for buffer program 2N times typical Maximum time out for individual Sector/Block-Erase 2N times typical (21 x 24 = 32 ms) Maximum time out for Chip-Erase 2N times typical (21 x 25 = 64 ms)
T6.3 1143
FOR
SST39VF320
TABLE 7: DEVICE GEOMETRY INFORMATION
Address 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H 32H 33H 34H Data 0016H 0001H 0000H 0000H 0000H 0002H 00FFH 0003H 0010H 0000H 003FH 0000H 0000H 0001H
FOR
SST39VF320
Data Device size = 2N Bytes (16H = 22; 222 = 4MByte) Flash Device Interface description; 0001H = x16-only asynchronous interface Maximum number of bytes in multi-byte write = 2N (00H = not supported) Number of Erase Sector/Block sizes supported by device Sector Information (y + 1 = Number of sectors; z x 256B = sector size) y = 1023 + 1 = 1024 sectors (03FFH = 1023) z = 16 x 256 Bytes = 4 KByte/sector (0010H = 16) Block Information (y + 1 = Number of blocks; z x 256B = block size) y = 63 + 1 = 64 blocks (0007H = 7) z = 256 x 256 Bytes = 64 KByte/block (0100H = 256)
T7.2 1143
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32 Mbit Multi-Purpose Flash SST39VF320
Preliminary Specifications Absolute Maximum Stress Ratings (Applied conditions greater than those listed under "Absolute Maximum Stress Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the operational sections of this data sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.) Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55C to +125C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to +150C D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to VDD + 0.5V Transient Voltage (<20 ns) on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1.0V to VDD + 1.0V Voltage on A9 and A21 Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 12.6V Package Power Dissipation Capability (Ta = 25C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W Surface Mount Lead Soldering Temperature (3 Seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240C Output Short Circuit Current1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
1. Outputs shorted for no more than one second. No more than one output shorted at a time.
OPERATING RANGE
Range Commercial Industrial Ambient Temp 0C to +70C -40C to +85C
OF
VDD 2.7-3.6V 2.7-3.6V
AC CONDITIONS
TEST
Input Rise/Fall Time . . . . . . . . . . . . . . 5 ns Output Load . . . . . . . . . . . . . . . . . . . . CL = 30 pF See Figures 14 and 15
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32 Mbit Multi-Purpose Flash SST39VF320
Preliminary Specifications TABLE 8: DC OPERATING CHARACTERISTICS VDD = 2.7-3.6V1
Limits Symbol IDD Parameter Power Supply Current Read2 Program and Erase ISB IALP ILI ILO VIL VIH VIHC VOL VOH Standby VDD Current Auto Low Power Current Input Leakage Current Output Leakage Current Input Low Voltage Input High Voltage Input High Voltage (CMOS) Output Low Voltage Output High Voltage VDD-0.2 0.7VDD VDD-0.3 0.2 18 35 20 20 1 10 0.8 V V V V mA mA A A A A Min Max Units Test Conditions Address input=VILT/VIHT, at f=5 MHz, VDD=VDD Max CE#=VIL, OE#=WE#=VIH, all I/Os open CE#=WE#=VIL, OE#=VIH CE#=VIHC, VDD=VDD Max CE#=VILC, VDD=VDD Max, all inputs=VSS or VDD, WE#=VIHC VIN=GND to VDD, VDD=VDD Max VOUT=GND to VDD, VDD=VDD Max VDD=VDD Min VDD=VDD Max VDD=VDD Max IOL=100 A, VDD=VDD Min IOH=-100 A, VDD=VDD Min
T8.11 1143
1. Typical conditions for the Active Current shown on the front page of the data sheet are average values at 25C (room temperature), and VDD = 3.0V. Not 100% tested. 2. The IDD current listed is typically less than 2mA/MHz, with OE# at VIH. Typical VDD is 3.0V.
TABLE 9: RECOMMENDED SYSTEM POWER-UP TIMINGS
Symbol TPU-READ
1
Parameter Power-up to Read Operation Power-up to Program/Erase Operation
Minimum 100 100
Units s s
T9.0 1143
TPU-WRITE1
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
TABLE 10: CAPACITANCE
Parameter CI/O1 CIN
1
(Ta = 25C, f=1 Mhz, other pins open)
Description I/O Pin Capacitance Input Capacitance
Test Condition VI/O = 0V VIN = 0V
Maximum 12 pF 6 pF
T10.0 1143
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
TABLE 11: RELIABILITY CHARACTERISTICS
Symbol NEND1,2 TDR1 ILTH1 Parameter Endurance Data Retention Latch Up Minimum Specification 10,000 100 100 + IDD Units Cycles Years mA Test Method JEDEC Standard A117 JEDEC Standard A103 JEDEC Standard 78
T11.3 1143
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. 2. NEND endurance rating is qualified as a 10,000 cycle minimum for the whole device. A sector- or block-level rating would result in a higher minimum specification.
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32 Mbit Multi-Purpose Flash SST39VF320
Preliminary Specifications
AC CHARACTERISTICS
TABLE 12: READ CYCLE TIMING PARAMETERS VDD = 2.7-3.6V
SST39VF320-70 Symbol TRC TCE TAA TOE TCLZ1 TOLZ1 TCHZ1 TOHZ1 TOH1 Parameter Read Cycle Time Chip Enable Access Time Address Access Time Output Enable Access Time CE# Low to Active Output OE# Low to Active Output CE# High to High-Z Output OE# High to High-Z Output Output Hold from Address Change 0 0 0 20 20 0 Min 70 70 70 35 0 0 30 30 Max SST39VF320-90 Min 90 90 90 45 Max Units ns ns ns ns ns ns ns ns ns
T12.1 1143
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
TABLE 13: PROGRAM/ERASE CYCLE TIMING PARAMETERS
Symbol TBP TAS TAH TCS TCH TOES TOEH TCP TWP TWPH1 TCPH TDS TDH TSE TBE TSCE
1 1
Parameter Word-Program Time Address Setup Time Address Hold Time WE# and CE# Setup Time WE# and CE# Hold Time OE# High Setup Time OE# High Hold Time CE# Pulse Width WE# Pulse Width WE# Pulse Width High CE# Pulse Width High Data Setup Time Data Hold Time Software ID Access and Exit Time Sector-Erase Block-Erase Chip-Erase
Min 0 30 0 0 0 10 40 40 30 30 30 0
Max 10
Units s ns ns ns ns ns ns ns ns ns ns ns ns
TIDA1
150 25 25 50
ns ms ms ms
T13.2 1143
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
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32 Mbit Multi-Purpose Flash SST39VF320
Preliminary Specifications
TRC ADDRESS A20-0
TAA
CE#
TCE
OE# VIH WE# TOLZ
TOE
TOHZ TCHZ HIGH-Z DATA VALID
DQ15-0
HIGH-Z
TCLZ
TOH DATA VALID
1143 F03.1
FIGURE 3: READ CYCLE TIMING DIAGRAM
INTERNAL PROGRAM OPERATION STARTS TBP ADDRESS A20-0 5555 TAH TWP WE# TAS OE# TCH CE# TCS DQ15-0 XXAA SW0 XX55 SW1 XXA0 SW2 DATA TWPH TDS 2AAA 5555 ADDR TDH
Note:
WORD (ADDR/DATA) X can be VIL or VIH, but no other value
1143 F04.2
FIGURE 4: WE# CONTROLLED PROGRAM CYCLE TIMING DIAGRAM
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32 Mbit Multi-Purpose Flash SST39VF320
Preliminary Specifications
INTERNAL PROGRAM OPERATION STARTS TBP ADDRESS A20-0 5555 TAH TCP CE# TAS OE# TCH WE# TCS DQ15-0 XXAA SW0 Note: XX55 SW1 XXA0 SW2 DATA WORD (ADDR/DATA) TCPH TDS 2AAA 5555 ADDR TDH
1143 F05.2
X can be VIL or VIH, but no other value
FIGURE 5: CE# CONTROLLED PROGRAM CYCLE TIMING DIAGRAM
ADDRESS A20-0 TCE CE# TOEH OE# TOE WE# TOES
DQ7
DATA
DATA#
DATA#
DATA
1143 F06.1
FIGURE 6: DATA# POLLING TIMING DIAGRAM
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32 Mbit Multi-Purpose Flash SST39VF320
Preliminary Specifications
ADDRESS A20-0 TCE CE# TOEH OE# TOE TOES
WE#
DQ6
TWO READ CYCLES WITH SAME OUTPUTS
1143 F07.1
FIGURE 7: TOGGLE BIT TIMING DIAGRAM
SIX-BYTE CODE FOR CHIP-ERASE ADDRESS A20-0 5555 2AAA 5555 5555 2AAA 5555
TSCE
CE#
OE# TWP WE#
DQ15-0
XXAA SW0
XX55 SW1
XX80 SW2
XXAA SW3
XX55 SW4
XX10 SW5
1143 F08.2
Note: This device also supports CE# controlled Chip-Erase operation. The WE# and CE# signals are interchageable as long as minimum timings are met. (See Table 13) X can be VIL or VIH, but no other value
FIGURE 8: WE# CONTROLLED CHIP-ERASE TIMING DIAGRAM
(c)2003 Silicon Storage Technology, Inc.
S71143-02-000
11/03
13
32 Mbit Multi-Purpose Flash SST39VF320
Preliminary Specifications
SIX-BYTE CODE FOR BLOCK-ERASE ADDRESS A20-0 5555 2AAA 5555 5555 2AAA BAX
TBE
CE#
OE# TWP WE#
DQ15-0
XXAA SW0
XX55 SW1
XX80 SW2
XXAA SW3
XX55 SW4
XX50 SW5
1143 F17.2
Note: This device also supports CE# controlled Block-Erase operation. The WE# and CE# signals are interchageable as long as minimum timings are met. (See Table 13) BAX = Block Address X can be VIL or VIH, but no other value
FIGURE 9: WE# CONTROLLED BLOCK-ERASE TIMING DIAGRAM
SIX-BYTE CODE FOR SECTOR-ERASE ADDRESS A20-0 5555 2AAA 5555 5555 2AAA SAX
TSE
CE#
OE# TWP WE#
DQ15-0
XXAA SW0
XX55 SW1
XX80 SW2
XXAA SW3
XX55 SW4
XX30 SW5
1143 F18.2
Note: This device also supports CE# controlled Sector-Erase operation. The WE# and CE# signals are interchageable as long as minimum timings are met. (See Table 13) SAX = Sector Address X can be VIL or VIH, but no other value
FIGURE 10: WE# CONTROLLED SECTOR-ERASE TIMING DIAGRAM
(c)2003 Silicon Storage Technology, Inc.
S71143-02-000
11/03
14
32 Mbit Multi-Purpose Flash SST39VF320
Preliminary Specifications
THREE-BYTE SEQUENCE FOR SOFTWARE ID ENTRY ADDRESS A14-0 5555 2AAA 5555 0000 0001
CE#
OE# TWP WE# TWPH DQ15-0 XXAA SW0 XX55 SW1 XX90 SW2 TAA 00BF Device ID
1143 F09.2
TIDA
Device ID = 2783H for SST39VF320 Note: X can be VIL or VIH, but no other value
FIGURE 11: SOFTWARE ID ENTRY
AND
READ
THREE-BYTE SEQUENCE FOR CFI QUERY ENTRY ADDRESS A14-0 5555 2AAA 5555
CE#
OE# TWP WE# TWPH DQ15-0 XXAA SW0 XX55 SW1 XX98 SW2
1143 F20.1
TIDA
TAA
Note: X can be VIL or VIH, but no other value
FIGURE 12: CFI QUERY ENTRY
AND
READ
(c)2003 Silicon Storage Technology, Inc.
S71143-02-000
11/03
15
32 Mbit Multi-Purpose Flash SST39VF320
Preliminary Specifications
THREE-BYTE SEQUENCE FOR SOFTWARE ID EXIT AND RESET
ADDRESS A14-0
5555
2AAA
5555
DQ15-0
XXAA
XX55
XXF0 TIDA
CE#
OE# TWP WE# T WHP SW0 SW1 SW2
1143 F10.1
Note: X can be VIL or VIH, but no other value
FIGURE 13: SOFTWARE ID EXIT/CFI EXIT
(c)2003 Silicon Storage Technology, Inc.
S71143-02-000
11/03
16
32 Mbit Multi-Purpose Flash SST39VF320
Preliminary Specifications
VIHT
INPUT
VIT
REFERENCE POINTS
VOT
OUTPUT
VILT
1143 F11.0
AC test inputs are driven at VIHT (0.9 VDD) for a logic "1" and VILT (0.1 VDD) for a logic "0". Measurement reference points for inputs and outputs are VIT (0.5 VDD) and VOT (0.5 VDD). Input rise and fall times (10% 90%) are <5 ns.
Note: VIT - VINPUT Test VOT - VOUTPUT Test VIHT - VINPUT HIGH Test VILT - VINPUT LOW Test
FIGURE 14: AC INPUT/OUTPUT REFERENCE WAVEFORMS
TO TESTER
TO DUT CL
1143 F12.0
FIGURE 15: A TEST LOAD EXAMPLE
(c)2003 Silicon Storage Technology, Inc.
S71143-02-000
11/03
17
32 Mbit Multi-Purpose Flash SST39VF320
Preliminary Specifications
Start
Load data: XXAAH Address: 5555H
Load data: XX55H Address: 2AAAH
Load data: XXA0H Address: 5555H
Load Word Address/Word Data
Wait for end of Program (TBP, Data# Polling bit, or Toggle bit operation) Program Completed
1143 F13.2
X can be VIL or VIH, but no other value
FIGURE 16: WORD-PROGRAM ALGORITHM
(c)2003 Silicon Storage Technology, Inc.
S71143-02-000
11/03
18
32 Mbit Multi-Purpose Flash SST39VF320
Preliminary Specifications
Internal Timer Program/Erase Initiated
Toggle Bit Program/Erase Initiated
Data# Polling Program/Erase Initiated
Wait TBP, TSCE, TSE or TBE
Read word
Read DQ7
Program/Erase Completed
Read same word
No
Is DQ7 = true data? Yes
No
Does DQ6 match? Yes Program/Erase Completed
Program/Erase Completed
1143 F14.0
FIGURE 17: WAIT OPTIONS
(c)2003 Silicon Storage Technology, Inc.
S71143-02-000
11/03
19
32 Mbit Multi-Purpose Flash SST39VF320
Preliminary Specifications
CFI Query Entry Command Sequence
Software ID Entry Command Sequence
Software ID Exit/CFI Exit Command Sequence
Load data: XXAAH Address: 5555H
Load data: XXAAH Address: 5555H
Load data: XXAAH Address: 5555H
Load data: XXF0H Address: XXH
Load data: XX55H Address: 2AAAH
Load data: XX55H Address: 2AAAH
Load data: XX55H Address: 2AAAH
Wait TIDA
Load data: XX98H Address: 5555H
Load data: XX90H Address: 5555H
Load data: XXF0H Address: 5555H
Return to normal operation
Wait TIDA
Wait TIDA
Wait TIDA
Read CFI data
Read Software ID
Return to normal operation
1143 F15.1
X can be VIL or VIH, but no other value
FIGURE 18: SOFTWARE ID/CFI COMMAND FLOWCHARTS
(c)2003 Silicon Storage Technology, Inc.
S71143-02-000
11/03
20
32 Mbit Multi-Purpose Flash SST39VF320
Preliminary Specifications
Chip-Erase Command Sequence Load data: XXAAH Address: 5555H
Sector-Erase Command Sequence Load data: XXAAH Address: 5555H
Block-Erase Command Sequence Load data: XXAAH Address: 5555H
Load data: XX55H Address: 2AAAH
Load data: XX55H Address: 2AAAH
Load data: XX55H Address: 2AAAH
Load data: XX80H Address: 5555H
Load data: XX80H Address: 5555H
Load data: XX80H Address: 5555H
Load data: XXAAH Address: 5555H
Load data: XXAAH Address: 5555H
Load data: XXAAH Address: 5555H
Load data: XX55H Address: 2AAAH
Load data: XX55H Address: 2AAAH
Load data: XX55H Address: 2AAAH
Load data: XX10H Address: 5555H
Load data: XX30H Address: SAX
Load data: XX50H Address: BAX
Wait TSCE
Wait TSE
Wait TBE
Chip erased to FFFFH
Sector erased to FFFFH
Block erased to FFFFH
1143 F16.1
X can be VIL or VIH, but no other value
FIGURE 19: ERASE COMMAND SEQUENCE
(c)2003 Silicon Storage Technology, Inc.
S71143-02-000
11/03
21
32 Mbit Multi-Purpose Flash SST39VF320
Preliminary Specifications
PRODUCT ORDERING INFORMATION
SST 39 XX VF XX 320 XXX - 70 - XXX 4C XX EK - XXX E X Environmental Attribute E = non-Pb Package Modifier K = 48 balls or leads Package Type B3 = TFBGA (0.8mm pitch, 6mm x 8mm) E = TSOP (type 1, die up, 12mm x 20mm) Temperature Range C = Commercial = 0C to +70C I = Industrial = -40C to +85C Minimum Endurance 4 = 10,000 cycles Read Access Speed 70 = 70 ns 90 = 90 ns Device Density 320 = 32 Mbit Voltage V = 2.7-3.6V Product Series 39 = Multi-Purpose Flash
Valid combinations for SST39VF320 SST39VF320-70-4C-EK SST39VF320-70-4C-EKE SST39VF320-90-4C-EK SST39VF320-90-4C-EKE SST39VF320-70-4I-EK SST39VF320-70-4I-EKE SST39VF320-90-4I-EK SST39VF320-90-4I-EKE SST39VF320-70-4C-B3K SST39VF320-70-4C-B3KE SST39VF320-90-4C-B3K SST39VF320-90-4C-B3KE SST39VF320-70-4I-B3K SST39VF320-70-4I-B3KE SST39VF320-90-4I-B3K SST39VF320-90-4I-B3KE
Note: Valid combinations are those products in mass production or will be in mass production. Consult your SST sales representative to confirm availability of valid combinations and to determine availability of new combinations.
(c)2003 Silicon Storage Technology, Inc.
S71143-02-000
11/03
22
32 Mbit Multi-Purpose Flash SST39VF320
Preliminary Specifications
PACKAGING DIAGRAMS
1.05 0.95 Pin # 1 Identifier 0.50 BSC
12.20 11.80
0.27 0.17
18.50 18.30
0.15 0.05
DETAIL 1.20 max. 0.70 0.50 20.20 19.80 0- 5 Note: 1. Complies with JEDEC publication 95 MO-142 DD dimensions, although some dimensions may be more stringent. 2. All linear dimensions are in millimeters (max/min). 3. Coplanarity: 0.1 mm 4. Maximum allowable mold flash is 0.15 mm at the package ends, and 0.25 mm between leads. 0.70 0.50
1mm 48-tsop-EK-8
48-LEAD THIN SMALL OUTLINE PACKAGE (TSOP) 12MM SST PACKAGE CODE: EK
X
20MM
(c)2003 Silicon Storage Technology, Inc.
S71143-02-000
11/03
23
32 Mbit Multi-Purpose Flash SST39VF320
Preliminary Specifications
TOP VIEW
8.00 0.20
BOTTOM VIEW
5.60 0.80 0.45 0.05 (48X)
6 5 4 3 2 1
0.80 ABCDEFGH A1 CORNER HGFEDCBA 4.00 6.00 0.20
6 5 4 3 2 1
SIDE VIEW
1.10 0.10
A1 CORNER
SEATING PLANE 0.35 0.05
0.12
1mm
Note:
1. Complies with JEDEC Publication 95, MO-210, variant 'AB-1', although some dimensions may be more stringent. 2. All linear dimensions are in millimeters. 3. Coplanarity: 0.12 mm 4. Ball opening size is 0.38 mm ( 0.05 mm) 48-tfbga-B3K-6x8-450mic-4
48-BALL THIN-PROFILE, FINE-PITCH BALL GRID ARRAY (TFBGA) 6MM SST PACKAGE CODE: B3K
X
8MM
TABLE 14: REVISION HISTORY
Number 00 01 02 Description Date Jan 2003 Mar 2003 Nov 2003
* * * * *
Initial release Clarified the Test Conditions for Power Supply Current parameter in Table 8 on page 9 2004 Data Book Updated the B3K package diagram Added non-Pb MPNs and removed footnote. (See page 22)
Silicon Storage Technology, Inc. * 1171 Sonora Court * Sunnyvale, CA 94086 * Telephone 408-735-9110 * Fax 408-735-9036 www.SuperFlash.com or www.sst.com
(c)2003 Silicon Storage Technology, Inc. S71143-02-000 11/03
24

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